集成运放综合参数测试仪

文档编号:CK058   文档字数:13418,页数:36

摘  要
 本系统参照片上系统的设计架构、采用FPGA与SPCE061A相结合的方法，以SPCE061A单片机为进程控制和任务调度核心；FPGA做为外围扩展，内部自建系统总线，地址译码采用全译码方式。FPGA内部建有DDS控制器，单片机通过系统总线向规定的存储单元中送入正弦表；然后DDS控制器以设定的频率，自动循环扫描，生成高精度，高稳定的5Hz基准测量信号。扫频信号通过对30MHz的FPGA系统时钟进行分频和外部锁相环（FPGA采用FLEX10K10无内部锁相环）倍频，产生高频率稳定度、幅值稳定度的扫频信号。放大器参数测量参照GB3442-82标准，低频信号幅度的测量采取AD高速采样，然后进行数字处理的方法；高频信号的幅度直接采用集成有效值转换芯片测得。A/D转换采用SPCE061A内部自带的10位AD。SPCE061A主要实现用户接口界面（键盘扫描、液晶显示、数据打印以及其他服务进程的调度）、AD转换以及测量参数（Vio Iio Kcmr Avd BWG Tr）计算、与上位机通信等方面的功能。上位机主要实现向下位机发送测量指令、与下位机交换测量数据、以及数据的存储、回放、统计。

关键词：参数测量、运算放大器、DDS、FPGA、SPCE061A、数字信号处理

Abstract
The system with reference to the design of system-on-chip architecture, used a combination of FPGA and SPCE061A approach to the process of SPCE061A single chip core control and task scheduling; FPGA for external expansion, internal self-system bus, address decoding the full translation code approach. There DDS internal FPGA controller, microcontroller through the system bus to the provisions of the storage unit into the sine table; DDS controller and then to set the frequency, automatic cycle of scanning, to generate high precision and high stability of the baseline measurement 5Hz signal. Sweep signal of 30MHz for the FPGA system clock frequency and external phase-locked loop (FPGA using FLEX10K10 no internal phase-locked loop) frequency, high frequency stability, amplitude stability of the sweep signal. Amplifier parameters measured by reference to the standard GB3442-82, low-frequency signal amplitude measurements taken by sampling high-speed AD and then proceed to the method of digital processing; high-frequency signal directly proportional to the magnitude of the integrated chip measured RMS conversion. A / D conversion using internal SPCE061A own 10 of the AD. SPCE061A main user interface (keyboard scanning, liquid crystal display, data printing and other services for the activation process), AD conversion, and measurement parameters (Vio Iio Kcmr Avd BWG Tr), the host computer and communications functions. PC main crew sent down measurement instructions, and under the exchange of measurement data-bit machines, as well as data storage, playback, and Statistics.

Key words：measurement of operational, amplifier parameters, DDS, FPGA, SPCE061A, digital
signal processing

目 录
摘要……………………………………………………………………………….……………..I
Abstract………………………………………………………………………….…………….Ⅱ
1 前言…………………………………………………………………………………………..1
2 总体方案设计………………………………………………………………………………3
2.1  集成运算放大器的主要性能参数……………………………………………………3
2.2  系统方案比较设计与论证…………………………...…………………………….....3
 2.2.1  测量电路模块………………………………….……………………………...4
 2.2.2  信号采集模块…………………………………….……….......………………6
 2.2.3  用户接口模块………………………………………….……...………………6
2.3  整机工作原理与功能实现…………………………………………………...……….7
2.4  软件系统………………………………………………………………………………9
2.5  其他系统扩展…………………………………………………………………………11
3  各子模块的设计…………………………………………………………..……………...12
 3.1  输入电压4～40mV、输入电流0～4mA 量程转换………………………………….12
 3.2  静态参数与动态参数的测量………………………………………………...………12
 3.3  5Hz 4V 有效值正弦波的实现……………………………….………...………….…12
 3.4  单位增益带宽测试………………………………………………………………...…13
 3.5  自动测量功能的实现………………………………………………………………...14
 3.6  显示模块……………………………………………………………………………...14
 3.7  键盘模块……………………………………………………………………………...15
 3.8  UART-PC 机通讯……………………………………………………………...……...16
4  理论计算及分析……………………………………………………………………….....17
 4.1  开环放大倍数的测量……………………………………………………...…………17
 4.2  输入失调电压的测量…………………………...……………………………………18
 4.3  输入失调电流的测量………………………………………………………..……….19
 4.4  共模抑制比的测量…………………………………………………………………...20
 4.5  -3dB 带宽F0…………………………………………………………………………20
 4.6  转换速率(SR)和上升时间的测量……………………………………………….….21
5  电路图及有关设计文件………………………………………………………………..22
 5.1  电源电路…………………………………………………………………………….22
 5.2  单片机、FPGA 系统板电路………………………………………………………..23
5.3  测量电路……………………………………………………………….……………24
 5.4  精密整流电路……………………………………………………………………….24
 5.5  低通滤波电路………………………………………………………………………..25
6  系统测试…………………………...……………………………………………………...27
 6.1  测试仪器……………………………………………………………………………..27
 6.2  测试数据…………………………………………………………………..…………27
 6.3  抗干扰措施…………………………..………………………………………………28
7  总结………………………………………………………………………………………...30
致谢…………………………………………………………………………………………......31
参考文献…………………………………………………………………………………….....32

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